A*STAR Institute for High Performance Computing researchers say they have developed an efficient modeling technique that significantly decreases the amount of computing time needed to relay signals between electronic components. They note that there are two basic approaches to simulating the power and signal integrity of a wire network, one of which is to use exact equations to describe the power and supply networks, and the other approach involves using numerical methods. The A*STAR researchers used a hybrid approach to combine the benefits of analytical and computational models. They were able to include the signaling network, as well as loads attached to the circuit board. The model was tested on a case comprised of a multilayer circuit board that included multiple ground plates, signal traces, and vias linking different layers, and capacitors decoupling different power supply circuits. Both the new hybrid model and a numerical finite element model were used to calculate the reaction of the circuit board to input signals with frequencies up to 20 GHz. The hybrid model needed just 48 seconds of central processing unit time and 0.71 MB of computer memory to run, versus 1,960 seconds and 74.2 MB for the finite element approach.